52 lines
1.2 KiB
VHDL
52 lines
1.2 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.all;
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library work;
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entity demo is
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PORT(
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-- the system's clock
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clk: IN STD_LOGIC;
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-- outputs from byte display
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segments: out std_logic_vector(1 downto 0);
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leds: out std_logic_vector(6 downto 0);
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-- inputs from byte input
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switches: in std_logic_vector(7 downto 0);
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button: in std_LOGIC
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);
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end demo;
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architecture sim of demo is
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SIGNAL slow_clk: STD_LOGIC := '0';
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SIGNAL ram_clk: STD_LOGIC := '0';
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SIGNAL s_address:STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
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SIGNAL s_data_in: STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL s_data_out: STD_LOGIC_VECTOR (7 DOWNTO 0) := x"FF";
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SIGNAL s_wren: STD_LOGIC := '0';
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begin
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clock_divider: entity work.clock_divider_module generic map (
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scale_1 => 25000000,
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scale_2 => 25000000/4
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) port map (clk, slow_clk, ram_clk);
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input: entity work.byte_input port map (
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clk,
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s_data_out,
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switches,
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button
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);
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display: entity work.byte_display port map (
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clk => clk,
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reset => '0',
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write => slow_clk,
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enable => slow_clk,
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--data => "0000" & s_address,
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data => s_data_out,
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segments => segments,
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leds => leds
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);
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END sim;
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