LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;

library work;

entity demo is
    PORT(
			-- the system's clock
			clk: IN  STD_LOGIC;
			-- outputs from byte display
		  	segments: out std_logic_vector(1 downto 0);
			leds: out std_logic_vector(6 downto 0);
			-- inputs from byte input
			switches: in std_logic_vector(7 downto 0);
			button: in std_LOGIC
	 );
end demo;

architecture sim of demo is
	SIGNAL slow_clk: STD_LOGIC := '0';
	SIGNAL ram_clk: STD_LOGIC := '0';
	
	SIGNAL s_address:STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
	SIGNAL s_data_in: STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL s_data_out: STD_LOGIC_VECTOR (7 DOWNTO 0) := x"FF";
	SIGNAL s_wren: STD_LOGIC := '0';
begin
		clock_divider: entity work.clock_divider_module generic map (
			   scale_1 => 25000000,
            scale_2 => 25000000/4
		) port map (clk, slow_clk, ram_clk);
		
	input: entity work.byte_input port map (
		clk,
		s_data_out,
		switches,
		button
	);

	display: entity work.byte_display port map (
		clk => clk,
      reset => '0',
		write => slow_clk,
		enable => slow_clk,
		--data => "0000" & s_address,
		data => s_data_out,
		segments => segments,
		leds => leds
	);
END sim;