add vhdl code
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity byte_display is
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port(
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clk: in std_logic;
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reset: in std_logic;
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write: in std_logic;
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enable: in std_logic;
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data: in std_logic_vector(7 downto 0);
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segments: out std_logic_vector(1 downto 0);
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leds: out std_logic_vector(6 downto 0)
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);
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end byte_display;
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architecture bhv of byte_display is
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procedure display_digit(
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signal digit: in std_logic_vector (3 downto 0);
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signal leds: out std_logic_vector(6 downto 0)
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) is
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begin
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case digit is -- GFEDCBA
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when "0000" => leds <= "0111111"; -- 0 ABCDEF
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when "0001" => leds <= "0000110"; -- 1 BC
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when "0010" => leds <= "1011011"; -- 2 ABDEG
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when "0011" => leds <= "1001111"; -- 3 ABCDG
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when "0100" => leds <= "1100110"; -- 4 BCFG
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when "0101" => leds <= "1101101"; -- 5 ACDFG
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when "0110" => leds <= "1111101"; -- 6 ACDEFG
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when "0111" => leds <= "0000111"; -- 7 ABC
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when "1000" => leds <= "1111111"; -- 8 ABCDEFG
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when "1001" => leds <= "1101111"; -- 9 ABCDFG
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when "1010" => leds <= "1110111"; -- A ABCEFG
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when "1011" => leds <= "1111100"; -- B CDEFG
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when "1100" => leds <= "1011000"; -- C DEG
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when "1101" => leds <= "1011110"; -- D BCDEG
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when "1110" => leds <= "1111001"; -- E ADEFG
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when "1111" => leds <= "1110001"; -- F AEFG
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when others => leds <= (others => '0');
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end case;
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end display_digit;
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type digits_type is array (1 downto 0) of std_logic_vector (3 downto 0);
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signal digits: digits_type;
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begin
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-- update internal byte
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process(clk, reset)
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begin
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if reset = '1' then
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digits(0) <= (others => '0');
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digits(1) <= (others => '0');
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elsif reset = '0' and rising_edge(clk) then
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if enable = '1' and write = '1' then
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for i in 0 to 1 loop
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-- digits sind ein internes Signal
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digits(i) <= data(((4*i)+3) downto (4*i));
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end loop;
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end if;
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end if;
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end process;
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process(clk, digits)
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variable digit_cntr : integer := 0;
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variable digit : integer := 0;
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begin
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-- select proper digit
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if rising_edge(clk) then
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digit_cntr := digit_cntr + 1;
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if (digit_cntr > 50000) then
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digit_cntr := 0;
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digit := digit + 1;
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if (digit > 1) then
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digit := 0;
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end if;
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end if;
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end if;
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-- display the nibble
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if (digit = 0) then
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segments <= "01";
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display_digit(digits(0),leds);
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else
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segments <= "10";
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display_digit(digits(1),leds);
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end if;
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end process;
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end bhv;
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@ -0,0 +1,29 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity byte_input is
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PORT(
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clk: in std_logic;
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data: out std_logic_vector(7 downto 0);
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switches: in std_logic_vector(7 downto 0);
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button: in std_logic
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);
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end byte_input;
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architecture sim of byte_input is
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signal s_button: std_logic;
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begin
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debouncer: entity work.debounce
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port map (
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clk => clk,
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button => not button,
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result => s_button
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);
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process(clk)
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begin
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if rising_edge(clk) and s_button = '1' then
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data <= switches;
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end if;
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end process;
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end sim;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY clock_divider_module IS
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GENERIC (
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scale_1: INTEGER;
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scale_2: INTEGER
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);
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PORT (
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clk: IN std_logic;
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clock_out_1: OUT std_logic;
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clock_out_2: OUT std_logic
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);
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END clock_divider_module;
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ARCHITECTURE behavior_clock_divider_module OF clock_divider_module IS
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signal counter_1: integer range 0 to (scale_1 - 1) := 0;
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signal slow_1: std_logic := '0';
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signal counter_2: integer range 0 to (scale_2 - 1) := 0;
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signal slow_2: std_logic := '0';
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begin
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clock_out_1 <= slow_1;
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clock_out_2 <= slow_2;
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process(clk)
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begin
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if rising_edge(clk) then
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if (counter_1 = (scale_1 - 1)) then
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slow_1 <= '1';
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counter_1 <= 0;
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else
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slow_1 <= '0';
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counter_1 <= counter_1 + 1;
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end if;
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if (counter_2 = (scale_2 - 1)) then
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slow_2 <= '1';
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counter_2 <= 0;
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else
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slow_2 <= '0';
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counter_2 <= counter_2 + 1;
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end if;
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end if;
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end process;
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end behavior_clock_divider_module;
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--------------------------------------------------------------------------------
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--
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-- FileName: debounce.vhd
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-- Dependencies: none
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-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
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--
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-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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--
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-- Version History
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-- Version 1.0 3/26/2012 Scott Larson
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-- Initial Public Release
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--
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-- Taken from https://eewiki.net/pages/viewpage.action?pageId=4980758
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY debounce IS
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GENERIC(
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counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
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PORT(
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clk : IN STD_LOGIC; --input clock
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button : IN STD_LOGIC; --input signal to be debounced
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result : OUT STD_LOGIC); --debounced signal
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END debounce;
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ARCHITECTURE logic OF debounce IS
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SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
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SIGNAL counter_set : STD_LOGIC; --sync reset to zero
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SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
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BEGIN
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counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
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PROCESS(clk)
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BEGIN
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IF(clk'EVENT and clk = '1') THEN
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flipflops(0) <= button;
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flipflops(1) <= flipflops(0);
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If(counter_set = '1') THEN --reset counter because input is changing
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counter_out <= (OTHERS => '0');
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ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
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counter_out <= std_logic_vector(unsigned(counter_out) + 1);
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ELSE --stable input time is met
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result <= flipflops(1);
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END IF;
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END IF;
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END PROCESS;
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END logic;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.all;
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library work;
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entity demo is
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PORT(
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-- the system's clock
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clk: IN STD_LOGIC;
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-- outputs from byte display
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segments: out std_logic_vector(1 downto 0);
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leds: out std_logic_vector(6 downto 0);
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-- inputs from byte input
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switches: in std_logic_vector(7 downto 0);
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button: in std_LOGIC
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);
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end demo;
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architecture sim of demo is
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SIGNAL slow_clk: STD_LOGIC := '0';
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SIGNAL ram_clk: STD_LOGIC := '0';
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SIGNAL s_address:STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
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SIGNAL s_data_in: STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL s_data_out: STD_LOGIC_VECTOR (7 DOWNTO 0) := x"FF";
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SIGNAL s_wren: STD_LOGIC := '0';
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begin
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clock_divider: entity work.clock_divider_module generic map (
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scale_1 => 25000000,
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scale_2 => 25000000/4
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) port map (clk, slow_clk, ram_clk);
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input: entity work.byte_input port map (
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clk,
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s_data_out,
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switches,
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button
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);
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display: entity work.byte_display port map (
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clk => clk,
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reset => '0',
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write => slow_clk,
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enable => slow_clk,
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--data => "0000" & s_address,
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data => s_data_out,
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segments => segments,
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leds => leds
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);
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END sim;
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