jlusiardi/vhdl_7seg
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Joachim Lusiardi c2f7969f85 add hw design
2018-04-09 18:45:47 +02:00
hardware
add hw design
2018-04-09 18:45:47 +02:00
byte_display.vhd
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2018-02-26 19:52:31 +01:00
debounce.vhd
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2018-02-26 19:52:31 +01:00
LICENSE
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2018-02-26 18:49:52 +00:00
main.vhd
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README.md
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2018-02-26 18:49:52 +00:00
vhdl7seg_tb.vhd
first version
2018-02-26 19:52:31 +01:00

README.md

vhdl_7seg

Git repository for blog article https://www.lusiardi.de/1148/fpga-7-segmentanzeige/

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Description
Git repository for blog article https://www.lusiardi.de/1148/fpga-7-segmentanzeige/ https://www.lusiardi.de/1148/fpga-7-segmentanzeige/
Readme 172 KiB
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VHDL 100%