jlusiardi/vhdl_7seg
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
3 Commits 1 Branch 0 Tags
master
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Joachim Lusiardi c2f7969f85 add hw design
2018-04-09 18:45:47 +02:00
hardware
add hw design
2018-04-09 18:45:47 +02:00
byte_display.vhd
first version
2018-02-26 19:52:31 +01:00
debounce.vhd
first version
2018-02-26 19:52:31 +01:00
LICENSE
Initial commit
2018-02-26 18:49:52 +00:00
main.vhd
first version
2018-02-26 19:52:31 +01:00
README.md
Initial commit
2018-02-26 18:49:52 +00:00
vhdl7seg_tb.vhd
first version
2018-02-26 19:52:31 +01:00

README.md

vhdl_7seg

Git repository for blog article https://www.lusiardi.de/1148/fpga-7-segmentanzeige/

Reference in New Issue View Git Blame Copy Permalink
Description
Git repository for blog article https://www.lusiardi.de/1148/fpga-7-segmentanzeige/ https://www.lusiardi.de/1148/fpga-7-segmentanzeige/
Readme 172 KiB
Languages
VHDL 100%