59 lines
1.3 KiB
VHDL
59 lines
1.3 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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ENTITY main IS
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PORT(
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clk: in std_logic;
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btn: in std_logic;
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reset: in std_logic;
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segments: out std_logic_vector(1 downto 0);
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leds: out std_logic_vector(6 downto 0)
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);
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END main;
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ARCHITECTURE behavior OF main IS
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COMPONENT byte_display
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PORT(
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clk: in std_logic;
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enable: in std_logic;
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data: in std_logic_vector(7 downto 0);
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segments: out std_logic_vector(1 downto 0);
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leds: out std_logic_vector(6 downto 0)
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);
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END COMPONENT;
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COMPONENT debounce
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GENERIC(
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counter_size : INTEGER := 19
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);
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PORT(
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clk : IN STD_LOGIC;
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button : IN STD_LOGIC;
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result : OUT STD_LOGIC
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);
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END COMPONENT;
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--signal enable: std_logic := '1';
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signal data: std_logic_vector(7 downto 0) := (others => '0');
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signal buttons: std_logic_vector(1 downto 0) := (others => '0');
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BEGIN
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db: debounce port map(clk, not btn, buttons(0));
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db_1: debounce port map(clk, not reset, buttons(1));
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seg: byte_display port map(clk, clk, data, segments, leds);
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process(clk, buttons)
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variable counter : integer range 0 to 255;
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begin
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if buttons(1) = '1' then
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counter := 0;
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elsif rising_edge(buttons(0)) then
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counter := counter + 1;
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end if;
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data <= std_logic_vector(to_unsigned(counter, data'length));
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end process;
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END;
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