LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

ENTITY main IS 
	PORT(
		clk: in std_logic;
		btn: in std_logic;
		reset: in std_logic;
		segments: out std_logic_vector(1 downto 0);
		leds: out std_logic_vector(6 downto 0)
	);
END main;

ARCHITECTURE behavior OF main IS
	COMPONENT byte_display 
		PORT(
			clk: in std_logic;
			enable: in std_logic;
			data: in std_logic_vector(7 downto 0);
			segments: out std_logic_vector(1 downto 0);
			leds: out std_logic_vector(6 downto 0)
		);
	END COMPONENT;
	
	COMPONENT debounce
		GENERIC(
			counter_size  :  INTEGER := 19
		); 
		PORT(
			clk     : IN  STD_LOGIC;  
			button  : IN  STD_LOGIC;  
			result  : OUT STD_LOGIC
		);
	END COMPONENT;

	--signal enable: std_logic := '1';
	signal data: std_logic_vector(7 downto 0) := (others => '0');
	signal buttons: std_logic_vector(1 downto 0) := (others => '0');
	
BEGIN
	db: debounce port map(clk, not btn, buttons(0));
	db_1: debounce port map(clk, not reset, buttons(1));
	seg: byte_display port map(clk, clk, data, segments, leds);
	
	process(clk, buttons)
		variable counter : integer range 0 to 255;
	begin
		if buttons(1) = '1' then
			counter := 0;
      elsif rising_edge(buttons(0)) then
			counter := counter + 1;
		end if;

		data <= std_logic_vector(to_unsigned(counter, data'length));
	end process;
END;