58 lines
1.5 KiB
VHDL
58 lines
1.5 KiB
VHDL
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-- Library declarations: Add/change as needed
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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-- entity declaration for your my_andbench. Don't declare any ports here
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ENTITY vhdl7seg_tb IS
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END vhdl7seg_tb;
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ARCHITECTURE behavior OF vhdl7seg_tb IS
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-- Component Declaration: Unit Under my_and (UUT)
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COMPONENT vhdl7seg -- Replace 'my_and' with the name of the module to be my_anded.
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GENERIC (MAX: integer := 25000000);
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PORT( -- copy and paste the input and output ports of the UUT
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clk: in std_logic;
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enable: in std_logic;
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data: in std_logic_vector(7 downto 0);
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segments: out std_logic_vector(1 downto 0);
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leds: out std_logic_vector(6 downto 0)
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);
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END COMPONENT;
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--Signal definitions: Declare (and initialize) a signal for each port of the UUT.
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signal seg: STD_LOGIC;
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signal led: STD_LOGIC;
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-- Clock definitions
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signal clk: std_logic := '0';
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constant clk_period : time := 10 ps;
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BEGIN
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-- Clock process (toggle clock after each full period)
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clk_process :process
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begin
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clk <= not(clk);
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wait for clk_period/2;
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end process;
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-- Instantiate the Unit Under my_and (UUT).
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-- In the port map, connect with the coresponding signals you declared above.
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uut: vhdl7seg
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GENERIC MAP ( MAX => 1)
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PORT MAP (
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clk, seg, led
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);
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-- Stimulus process
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stim_proc: process
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begin
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wait for clk_period;
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end process;
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END;
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