60 lines
2.5 KiB
VHDL
60 lines
2.5 KiB
VHDL
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--
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-- FileName: debounce.vhd
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-- Dependencies: none
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-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
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--
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-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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--
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-- Version History
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-- Version 1.0 3/26/2012 Scott Larson
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-- Initial Public Release
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--
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-- Taken from https://eewiki.net/pages/viewpage.action?pageId=4980758
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY debounce IS
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GENERIC(
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counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
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PORT(
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clk : IN STD_LOGIC; --input clock
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button : IN STD_LOGIC; --input signal to be debounced
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result : OUT STD_LOGIC); --debounced signal
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END debounce;
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ARCHITECTURE logic OF debounce IS
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SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
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SIGNAL counter_set : STD_LOGIC; --sync reset to zero
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SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
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BEGIN
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counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
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PROCESS(clk)
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BEGIN
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IF(clk'EVENT and clk = '1') THEN
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flipflops(0) <= button;
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flipflops(1) <= flipflops(0);
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If(counter_set = '1') THEN --reset counter because input is changing
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counter_out <= (OTHERS => '0');
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ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
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counter_out <= std_logic_vector(unsigned(counter_out) + 1);
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ELSE --stable input time is met
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result <= flipflops(1);
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END IF;
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END IF;
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END PROCESS;
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END logic;
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