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vhdl_byte_input
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some improvements

This commit is contained in:
Joachim Lusiardi 2018-04-11 21:55:36 +02:00
parent a6bc95b557
commit 32c82ab469
2 changed files with 10 additions and 6 deletions
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7
byte_input.vhd
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@ -4,15 +4,18 @@ use IEEE.STD_LOGIC_1164.ALL;
entity byte_input is entity byte_input is
PORT( PORT(
clk: in std_logic; clk: in std_logic;
data: out std_logic_vector(7 downto 0);
switches: in std_logic_vector(7 downto 0); switches: in std_logic_vector(7 downto 0);
button: in std_logic button: in std_logic;
data: out std_logic_vector(7 downto 0);
act: out std_logic
); );
end byte_input; end byte_input;
architecture sim of byte_input is architecture sim of byte_input is
signal s_button: std_logic; signal s_button: std_logic;
begin begin
act <= s_button;
debouncer: entity work.debounce debouncer: entity work.debounce
port map ( port map (
clk => clk, clk => clk,

7
demo.vhd
View File

@ -24,7 +24,7 @@ architecture sim of demo is
SIGNAL s_address:STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"; SIGNAL s_address:STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL s_data_in: STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL s_data_in: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL s_data_out: STD_LOGIC_VECTOR (7 DOWNTO 0) := x"FF"; SIGNAL s_data_out: STD_LOGIC_VECTOR (7 DOWNTO 0) := x"FF";
SIGNAL s_wren: STD_LOGIC := '0'; SIGNAL s_act: STD_LOGIC;
begin begin
clock_divider: entity work.clock_divider_module generic map ( clock_divider: entity work.clock_divider_module generic map (
scale_1 => 25000000, scale_1 => 25000000,
@ -33,9 +33,10 @@ begin
input: entity work.byte_input port map ( input: entity work.byte_input port map (
clk, clk,
s_data_out,
switches, switches,
button button,
s_data_out,
s_act
); );
display: entity work.byte_display port map ( display: entity work.byte_display port map (