diff --git a/byte_input.vhd b/byte_input.vhd
index 4f0367d..d47f594 100644
--- a/byte_input.vhd
+++ b/byte_input.vhd
@@ -4,15 +4,18 @@ use IEEE.STD_LOGIC_1164.ALL;
 entity byte_input is
     PORT(
 			clk:      in std_logic;
-			data:     out std_logic_vector(7 downto 0);
 			switches: in std_logic_vector(7 downto 0);
-			button:   in std_logic
+			button:   in std_logic;
+			data:     out std_logic_vector(7 downto 0);
+			act:      out std_logic
 		);
 end byte_input;
 
 architecture sim of byte_input is
 	signal s_button: std_logic;
 begin
+	act <= s_button;
+
 	debouncer: entity work.debounce
 		port map (
 			clk => clk,
@@ -26,4 +29,4 @@ begin
 			data <= switches;
 		end if;
 	end process;
-end sim;
\ No newline at end of file
+end sim;
diff --git a/demo.vhd b/demo.vhd
index ca9c05e..427d5ac 100644
--- a/demo.vhd
+++ b/demo.vhd
@@ -24,7 +24,7 @@ architecture sim of demo is
 	SIGNAL s_address:STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
 	SIGNAL s_data_in: STD_LOGIC_VECTOR (7 DOWNTO 0);
 	SIGNAL s_data_out: STD_LOGIC_VECTOR (7 DOWNTO 0) := x"FF";
-	SIGNAL s_wren: STD_LOGIC := '0';
+    SIGNAL s_act: STD_LOGIC;
 begin
 		clock_divider: entity work.clock_divider_module generic map (
 			   scale_1 => 25000000,
@@ -33,9 +33,10 @@ begin
 		
 	input: entity work.byte_input port map (
 		clk,
-		s_data_out,
 		switches,
-		button
+		button,
+		s_data_out,
+        s_act
 	);
 
 	display: entity work.byte_display port map (