jlusiardi
/
vhdl_byte_input
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

some improvements

This commit is contained in:
Joachim Lusiardi 2018-04-11 21:55:36 +02:00
parent a6bc95b557
commit 32c82ab469
2 changed files with 10 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
byte_input.vhd
View File

@ -4,15 +4,18 @@ use IEEE.STD_LOGIC_1164.ALL;
entity byte_input is
PORT(
clk: in std_logic;
data: out std_logic_vector(7 downto 0);
switches: in std_logic_vector(7 downto 0);
button: in std_logic
button: in std_logic;
data: out std_logic_vector(7 downto 0);
act: out std_logic
);
end byte_input;
architecture sim of byte_input is
signal s_button: std_logic;
begin
act <= s_button;
debouncer: entity work.debounce
port map (
clk => clk,
@ -26,4 +29,4 @@ begin
data <= switches;
end if;
end process;
end sim;
end sim;

7
demo.vhd
View File

@ -24,7 +24,7 @@ architecture sim of demo is
SIGNAL s_address:STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL s_data_in: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL s_data_out: STD_LOGIC_VECTOR (7 DOWNTO 0) := x"FF";
SIGNAL s_wren: STD_LOGIC := '0';
SIGNAL s_act: STD_LOGIC;
begin
clock_divider: entity work.clock_divider_module generic map (
scale_1 => 25000000,
@ -33,9 +33,10 @@ begin
input: entity work.byte_input port map (
clk,
s_data_out,
switches,
button
button,
s_data_out,
s_act
);
display: entity work.byte_display port map (