44 lines
1016 B
VHDL
44 lines
1016 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY clock_divider_module IS
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GENERIC (
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scale_1: INTEGER;
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scale_2: INTEGER
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);
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PORT (
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clk: IN std_logic;
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clock_out_1: OUT std_logic;
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clock_out_2: OUT std_logic
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);
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END clock_divider_module;
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ARCHITECTURE behavior_clock_divider_module OF clock_divider_module IS
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signal counter_1: integer range 0 to (scale_1 - 1) := 0;
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signal slow_1: std_logic := '0';
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signal counter_2: integer range 0 to (scale_2 - 1) := 0;
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signal slow_2: std_logic := '0';
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begin
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clock_out_1 <= slow_1;
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clock_out_2 <= slow_2;
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process(clk)
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begin
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if rising_edge(clk) then
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if (counter_1 = (scale_1 - 1)) then
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slow_1 <= '1';
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counter_1 <= 0;
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else
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slow_1 <= '0';
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counter_1 <= counter_1 + 1;
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end if;
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if (counter_2 = (scale_2 - 1)) then
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slow_2 <= '1';
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counter_2 <= 0;
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else
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slow_2 <= '0';
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counter_2 <= counter_2 + 1;
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end if;
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end if;
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end process;
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end behavior_clock_divider_module;
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