33 lines
595 B
VHDL
33 lines
595 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity byte_input is
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PORT(
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clk: in std_logic;
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switches: in std_logic_vector(7 downto 0);
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button: in std_logic;
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data: out std_logic_vector(7 downto 0);
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act: out std_logic
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);
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end byte_input;
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architecture sim of byte_input is
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signal s_button: std_logic;
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begin
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act <= s_button;
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debouncer: entity work.debounce
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port map (
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clk => clk,
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button => not button,
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result => s_button
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);
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process(clk)
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begin
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if rising_edge(clk) and s_button = '1' then
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data <= switches;
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end if;
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end process;
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end sim;
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