vhdl_byte_input/byte_display.vhd

92 lines
2.4 KiB
VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity byte_display is
port(
clk: in std_logic;
reset: in std_logic;
write: in std_logic;
enable: in std_logic;
data: in std_logic_vector(7 downto 0);
segments: out std_logic_vector(1 downto 0);
leds: out std_logic_vector(6 downto 0)
);
end byte_display;
architecture bhv of byte_display is
procedure display_digit(
signal digit: in std_logic_vector (3 downto 0);
signal leds: out std_logic_vector(6 downto 0)
) is
begin
case digit is -- GFEDCBA
when "0000" => leds <= "0111111"; -- 0 ABCDEF
when "0001" => leds <= "0000110"; -- 1 BC
when "0010" => leds <= "1011011"; -- 2 ABDEG
when "0011" => leds <= "1001111"; -- 3 ABCDG
when "0100" => leds <= "1100110"; -- 4 BCFG
when "0101" => leds <= "1101101"; -- 5 ACDFG
when "0110" => leds <= "1111101"; -- 6 ACDEFG
when "0111" => leds <= "0000111"; -- 7 ABC
when "1000" => leds <= "1111111"; -- 8 ABCDEFG
when "1001" => leds <= "1101111"; -- 9 ABCDFG
when "1010" => leds <= "1110111"; -- A ABCEFG
when "1011" => leds <= "1111100"; -- B CDEFG
when "1100" => leds <= "1011000"; -- C DEG
when "1101" => leds <= "1011110"; -- D BCDEG
when "1110" => leds <= "1111001"; -- E ADEFG
when "1111" => leds <= "1110001"; -- F AEFG
when others => leds <= (others => '0');
end case;
end display_digit;
type digits_type is array (1 downto 0) of std_logic_vector (3 downto 0);
signal digits: digits_type;
begin
-- update internal byte
process(clk, reset)
begin
if reset = '1' then
digits(0) <= (others => '0');
digits(1) <= (others => '0');
elsif reset = '0' and rising_edge(clk) then
if enable = '1' and write = '1' then
for i in 0 to 1 loop
-- digits sind ein internes Signal
digits(i) <= data(((4*i)+3) downto (4*i));
end loop;
end if;
end if;
end process;
process(clk, digits)
variable digit_cntr : integer := 0;
variable digit : integer := 0;
begin
-- select proper digit
if rising_edge(clk) then
digit_cntr := digit_cntr + 1;
if (digit_cntr > 50000) then
digit_cntr := 0;
digit := digit + 1;
if (digit > 1) then
digit := 0;
end if;
end if;
end if;
-- display the nibble
if (digit = 0) then
segments <= "01";
display_digit(digits(0),leds);
else
segments <= "10";
display_digit(digits(1),leds);
end if;
end process;
end bhv;