LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY clock_divider_module IS
    GENERIC (
        scale_1: INTEGER;
        scale_2: INTEGER
    );
    PORT (
        clk: IN std_logic;
        clock_out_1: OUT std_logic;
        clock_out_2: OUT std_logic
    );
END clock_divider_module;

ARCHITECTURE behavior_clock_divider_module  OF clock_divider_module IS
	signal counter_1:   integer range 0 to (scale_1 - 1) := 0;
	signal slow_1:      std_logic := '0';
	signal counter_2:   integer range 0 to (scale_2 - 1) := 0;
	signal slow_2:      std_logic := '0';
begin
	clock_out_1 <= slow_1;
	clock_out_2 <= slow_2;
	process(clk)
	begin
		if rising_edge(clk) then
			if (counter_1 = (scale_1 - 1)) then
				slow_1 <= '1';
				counter_1 <= 0;
			else
				slow_1 <= '0';
				counter_1 <= counter_1 + 1;
			end if;
			if (counter_2 = (scale_2 - 1)) then
				slow_2 <= '1';
				counter_2 <= 0;
			else
				slow_2 <= '0';
				counter_2 <= counter_2 + 1;
			end if;
		end if;
	end process;
end behavior_clock_divider_module;