library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity byte_input is
    PORT(
			clk:      in std_logic;
			switches: in std_logic_vector(7 downto 0);
			button:   in std_logic;
			data:     out std_logic_vector(7 downto 0);
			act:      out std_logic
		);
end byte_input;

architecture sim of byte_input is
	signal s_button: std_logic;
begin
	act <= s_button;

	debouncer: entity work.debounce
		port map (
			clk => clk,
			button => not button,
			result => s_button
		);
	
	process(clk)
	begin
		if rising_edge(clk) and s_button = '1' then
			data <= switches;
		end if;
	end process;
end sim;