-- Library declarations: Add/change as needed
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

-- entity declaration for your my_andbench. Don't declare any ports here
ENTITY vhdl7seg_tb IS 
END vhdl7seg_tb;

ARCHITECTURE behavior OF vhdl7seg_tb IS
   -- Component Declaration: Unit Under my_and (UUT)
    COMPONENT vhdl7seg  -- Replace 'my_and' with the name of the module to be my_anded.
        GENERIC (MAX: integer := 25000000);
    PORT( -- copy and paste the input and output ports of the UUT
		clk: in std_logic;
		enable: in std_logic;
		data: in std_logic_vector(7 downto 0);
		segments: out std_logic_vector(1 downto 0);
		leds: out std_logic_vector(6 downto 0)
     );
    END COMPONENT;

   --Signal definitions: Declare (and initialize) a signal for each port of the UUT. 
        signal seg: STD_LOGIC;
        signal led: STD_LOGIC;
        

    -- Clock definitions
    signal clk: std_logic := '0';
    constant clk_period : time := 10 ps;

BEGIN

   -- Clock process (toggle clock after each full period)
   clk_process :process
   begin
        clk <= not(clk);
        wait for clk_period/2;
   end process;

  
-- Instantiate the Unit Under my_and (UUT).
-- In the port map, connect with the coresponding signals you declared above. 
   
   uut: vhdl7seg 
		GENERIC MAP ( MAX => 1)
		PORT MAP (
			clk, seg, led
		);
         
   -- Stimulus process
        stim_proc: process
   begin         
                        wait for clk_period;
        end process;

END;