From 6be9710b5277de37c7eaac31ca56123f130dd54f Mon Sep 17 00:00:00 2001 From: Joachim Lusiardi Date: Mon, 26 Feb 2018 19:52:31 +0100 Subject: [PATCH] first version --- byte_display.vhd | 82 ++++++++++++++++++++++++++++++++++++++++++++++++ debounce.vhd | 59 ++++++++++++++++++++++++++++++++++ main.vhd | 58 ++++++++++++++++++++++++++++++++++ vhdl7seg_tb.vhd | 57 +++++++++++++++++++++++++++++++++ 4 files changed, 256 insertions(+) create mode 100644 byte_display.vhd create mode 100644 debounce.vhd create mode 100644 main.vhd create mode 100644 vhdl7seg_tb.vhd diff --git a/byte_display.vhd b/byte_display.vhd new file mode 100644 index 0000000..91c3f6d --- /dev/null +++ b/byte_display.vhd @@ -0,0 +1,82 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity byte_display is + port( + clk: in std_logic; + enable: in std_logic; + data: in std_logic_vector(7 downto 0); + segments: out std_logic_vector(1 downto 0); + leds: out std_logic_vector(6 downto 0) + ); +end byte_display; + +architecture bhv of byte_display is + procedure display_digit( + signal digit: in std_logic_vector (3 downto 0); + signal leds: out std_logic_vector(6 downto 0) + ) is + begin + case digit is -- GFEDCBA + when "0000" => leds <= "0111111"; -- 0 ABCDEF + when "0001" => leds <= "0000110"; -- 1 BC + when "0010" => leds <= "1011011"; -- 2 ABDEG + when "0011" => leds <= "1001111"; -- 3 ABCDG + when "0100" => leds <= "1100110"; -- 4 BCFG + when "0101" => leds <= "1101101"; -- 5 ACDFG + when "0110" => leds <= "1111101"; -- 6 ACDEFG + when "0111" => leds <= "0000111"; -- 7 ABC + when "1000" => leds <= "1111111"; -- 8 ABCDEFG + when "1001" => leds <= "1101111"; -- 9 ABCDFG + when "1010" => leds <= "1110111"; -- A ABCEFG + when "1011" => leds <= "1111100"; -- B CDEFG + when "1100" => leds <= "1011000"; -- C DEG + when "1101" => leds <= "1011110"; -- D BCDEG + when "1110" => leds <= "1111001"; -- E ADEFG + when "1111" => leds <= "1110001"; -- F AEFG + end case; + end display_digit; + + type digits_type is array (1 downto 0) of std_logic_vector (3 downto 0); + signal digits: digits_type; + +begin + -- update internal byte + process(enable) + begin + if rising_edge(enable) then + for i in 0 to 1 loop + -- digits sind ein internes Signal + digits(i) <= data(((4*i)+3) downto (4*i)); + end loop; + end if; + end process; + + process(clk) + variable digit_cntr : integer := 0; + variable digit : integer := 0; + begin + -- select proper digit + if rising_edge(clk) then + digit_cntr := digit_cntr + 1; + if (digit_cntr > 50000) then + digit_cntr := 0; + digit := digit + 1; + if (digit > 1) then + digit := 0; + end if; + end if; + end if; + + -- display the nibble + if (digit = 0) then + segments <= "01"; + display_digit(digits(0),leds); + else + segments <= "10"; + display_digit(digits(1),leds); + end if; + end process; +end bhv; \ No newline at end of file diff --git a/debounce.vhd b/debounce.vhd new file mode 100644 index 0000000..4efeaca --- /dev/null +++ b/debounce.vhd @@ -0,0 +1,59 @@ +-------------------------------------------------------------------------------- +-- +-- FileName: debounce.vhd +-- Dependencies: none +-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version +-- +-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY +-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY +-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL +-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF +-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS +-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), +-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. +-- +-- Version History +-- Version 1.0 3/26/2012 Scott Larson +-- Initial Public Release +-- +-- Taken from https://eewiki.net/pages/viewpage.action?pageId=4980758 +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; + +ENTITY debounce IS + GENERIC( + counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock) + PORT( + clk : IN STD_LOGIC; --input clock + button : IN STD_LOGIC; --input signal to be debounced + result : OUT STD_LOGIC); --debounced signal +END debounce; + +ARCHITECTURE logic OF debounce IS + SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops + SIGNAL counter_set : STD_LOGIC; --sync reset to zero + SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output +BEGIN + + counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter + + PROCESS(clk) + BEGIN + IF(clk'EVENT and clk = '1') THEN + flipflops(0) <= button; + flipflops(1) <= flipflops(0); + If(counter_set = '1') THEN --reset counter because input is changing + counter_out <= (OTHERS => '0'); + ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met + counter_out <= counter_out + 1; + ELSE --stable input time is met + result <= flipflops(1); + END IF; + END IF; + END PROCESS; +END logic; diff --git a/main.vhd b/main.vhd new file mode 100644 index 0000000..c076ccb --- /dev/null +++ b/main.vhd @@ -0,0 +1,58 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +ENTITY main IS + PORT( + clk: in std_logic; + btn: in std_logic; + reset: in std_logic; + segments: out std_logic_vector(1 downto 0); + leds: out std_logic_vector(6 downto 0) + ); +END main; + +ARCHITECTURE behavior OF main IS + COMPONENT byte_display + PORT( + clk: in std_logic; + enable: in std_logic; + data: in std_logic_vector(7 downto 0); + segments: out std_logic_vector(1 downto 0); + leds: out std_logic_vector(6 downto 0) + ); + END COMPONENT; + + COMPONENT debounce + GENERIC( + counter_size : INTEGER := 19 + ); + PORT( + clk : IN STD_LOGIC; + button : IN STD_LOGIC; + result : OUT STD_LOGIC + ); + END COMPONENT; + + --signal enable: std_logic := '1'; + signal data: std_logic_vector(7 downto 0) := (others => '0'); + signal buttons: std_logic_vector(1 downto 0) := (others => '0'); + +BEGIN + db: debounce port map(clk, not btn, buttons(0)); + db_1: debounce port map(clk, not reset, buttons(1)); + seg: byte_display port map(clk, clk, data, segments, leds); + + process(clk, buttons) + variable counter : integer range 0 to 255; + begin + if buttons(1) = '1' then + counter := 0; + elsif rising_edge(buttons(0)) then + counter := counter + 1; + end if; + + data <= std_logic_vector(to_unsigned(counter, data'length)); + end process; +END; diff --git a/vhdl7seg_tb.vhd b/vhdl7seg_tb.vhd new file mode 100644 index 0000000..06cd0a0 --- /dev/null +++ b/vhdl7seg_tb.vhd @@ -0,0 +1,57 @@ +-- Library declarations: Add/change as needed +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; + +-- entity declaration for your my_andbench. Don't declare any ports here +ENTITY vhdl7seg_tb IS +END vhdl7seg_tb; + +ARCHITECTURE behavior OF vhdl7seg_tb IS + -- Component Declaration: Unit Under my_and (UUT) + COMPONENT vhdl7seg -- Replace 'my_and' with the name of the module to be my_anded. + GENERIC (MAX: integer := 25000000); + PORT( -- copy and paste the input and output ports of the UUT + clk: in std_logic; + enable: in std_logic; + data: in std_logic_vector(7 downto 0); + segments: out std_logic_vector(1 downto 0); + leds: out std_logic_vector(6 downto 0) + ); + END COMPONENT; + + --Signal definitions: Declare (and initialize) a signal for each port of the UUT. + signal seg: STD_LOGIC; + signal led: STD_LOGIC; + + + -- Clock definitions + signal clk: std_logic := '0'; + constant clk_period : time := 10 ps; + +BEGIN + + -- Clock process (toggle clock after each full period) + clk_process :process + begin + clk <= not(clk); + wait for clk_period/2; + end process; + + +-- Instantiate the Unit Under my_and (UUT). +-- In the port map, connect with the coresponding signals you declared above. + + uut: vhdl7seg + GENERIC MAP ( MAX => 1) + PORT MAP ( + clk, seg, led + ); + + -- Stimulus process + stim_proc: process + begin + wait for clk_period; + end process; + +END;